Electrostatic discharge (ESD) occurs when large voltage pulses due to static electricity occur at the leads of an integrated circuit (IC). These large voltage pulses can cause the breakdown of insulating layers, short circuiting between conducting paths, or overheating or evaporation of metal or silicon pathways within the IC leading to the failure of the IC. Increases in IC density have reduced the width of IC traces and the gate dielectric thickness of active devices which have made ICs more susceptible to damage from ESD events.
During the processing and handling of individual packaged ICs, circuits connected to external pins, or external bumps in some IC packages, can be exposed to very high voltages. Peripheral circuits therefore use special electrostatic discharge (ESD) protection circuits coupled to external pins. An input pin 112 with a conventional ESD protection device 116 and a buffer 114 is illustrated in FIG. 1. The ESD protection device 116 is a diode coupled to ground. Voltages above the breakdown voltage effectively short diode 116 and are thereby shunted to ground.
The continuous scaling of integrated circuits has enabled a rapid increase in IC operating frequencies. The parasitic capacitance of ESD protection circuits slows signals down and has made ESD circuits a major bottleneck for high-speed operation. In narrow-band designs, this capacitance can be resonated out with a package/bondwire inductance, and thereby circumvented. However, this approach is not applicable to broadband designs, and therefore the parasitic capacitance of ESD circuits continues to be a problem in conventional broadband designs. In high frequency ICs ESD devices are typically located as close to the input/output pads as possible. There are generally strict guidelines for the minimum metal width and the maximum distance from the ESD protection to the pads in order to minimize the voltage drop in the metal lines. Even slight non-uniformities in the via placement in ESD structures can cause severe performance degradation. This placement creates a large lumped capacitance due to the ESD protection at the pad. The ESD parasitic load becomes a significant problem around 1-2 GHz of operation; the reactance of the capacitance of a typical ESD protection circuit (1-2 pF) is almost as low as a 50 ohm transmission line. Therefore a significant part of the signal is lost through the ESD circuit. It is very difficult to make a resistive termination with such a large capacitive load. As a result, high frequency devices often do not include any ESD protection.
High frequency instruments using circuits without ESD protection require special care in order not to destroy the input buffers. Special grounding of operators/probes are usually required since the input circuits generally either have insufficient ESD protection or no ESD protection at all. The input circuits of high-frequency instruments such as spectrunm and network analyzers are particularly susceptible to ESD damage. As a result manufacturers typically make the input circuits easily replaceable. As the market for high frequency devices grows and as the operating frequencies of ICs continue to increase, protecting against ESD damage becomes increasingly important.
There is therefore a need for an improved ESD protection device with a sufficiently low parasitic capacitance to avoid reducing the bandwidth of high frequency devices.